What Is An xPU? - Semiconductor Engineering

Almost every day there is an announcement about a new processor architecture, and it is given a three-letter acronym — TPU, IPU, NPU. Home Systems&Design LowPower-HighPerformance Manufacturing,Packaging&Materials Test,Measurement&Analytics Auto,Security&PervasiveComputing SpecialReports Videos Jobs KnowledgeCenter TechnicalPapers Home'; AI/ML/DLArchitecturesAutomotiveCommunication/DataMovementDesign&VerificationLithographyManufacturingMaterialsMemoryOptoelectronicsPackagingPower&PerformanceQuantumSecurityTest&AnalyticsTransistors Events&Webinars Events Webinars Research&Startups IndustryResearch StartupCorner MENU Home SpecialReports Systems&Design LowPower-HighPerformance Manufacturing,Packaging&Materials Test,Measurement&Analytics Auto,Security&PervasiveComputing KnowledgeCenter Videos StartupCorner Jobs TechnicalPapers Events Webinars IndustryResearch SpecialReports Home> LowPower-HighPerformance> WhatIsAnxPU? LowPower-HighPerformance WhatIsAnxPU? Almosteveryletterofthealphabethasbeenusedtodescribeaprocessorarchitecture,butunderthehoodtheyalllookverysimilar. November11th, 2021- By:BrianBailey Almosteverydaythereisanannouncementaboutanewprocessorarchitecture,anditisgivenathree-letteracronym—TPU,IPU,NPU.Butwhatreallydistinguishesthem?Aretherereallythatmanyuniqueprocessorarchitectures,orissomethingelsehappening? In2018,JohnL.HennessyandDavidA.PattersondeliveredtheTuringlectureentitled,“ANewGoldenAgeforComputerArchitecture.”WhattheyconcentratedonwastheCPUandthewaythatithadevolved,butthatisonlyasmallpartofthetotalequation.“MostofthesethingsarenotreallyaprocessorinthesenseofbeingaCPU,”saysMichaelFrank,fellowandsystemarchitectatArterisIP.“They’remorelikeaGPU,anacceleratorforaspecialworkload,andthereisquiteabitofdiversitywithinthem.Machinelearningisaclassofprocessors,andyoujustcallthemallmachinelearningaccelerators,yetthereisalargevarietyofthepartoftheprocessingtheyaccelerate.” Theessenceofaprocessorcanbeboileddowntothreethings.“Attheendoftheday,itreallydoescomebacktotheinstructionsetarchitecture(ISA),”saysManuelUhm,directorforsiliconmarketingatXilinx.“Thatdefineswhatyou’retryingtodo.ThenyouhavetheI/Oandthememory,whichsupporttheISAandwhatit’stryingtoaccomplish.It’sgoingtobeareallyinterestingtimegoingforward,becausewearegoingseealotmoreinnovationandchangethanwe’veseeninthelasttwo-orthree-plusdecades.” Manyofthenewarchitecturesarenotsingleprocessors.“Whatweareseeingisacombinationofdifferenttypesofprocessors,orprogrammableengines,thatliveinthesameSoCorinthesamesystem,”saysPierre-XavierThomas,groupdirectorfortechnicalandstrategicmarketingatCadence.“Thereisdispatchingofthesoftwaretaskstodifferenthardwareorflexibleprogrammableengines.AlloftheprocessorsmayshareacommonAPI,buttheexecutiondomainisgoingtobedifferent.Thisisreallywhereyouwillseedifferenttypesofprocessingwithdifferenttypeofcharacteristics.” Therealityisthatmuchofthenamingismarketing.“Thekeythingisthatpeopleareusingthesenamesandacronymsfortwodifferentpurposes,”saysSimonDavidmann,CEOforImperasSoftware.“Oneisforexplainingthearchitectureofaprocessor,likeSIMD(singleinstructionmultipledata).Theotherdefinestheapplicationsegmentthatitisaddressing.Soitcandefineeithertheprocessorarchitecture,orabrandnamelikeTensorProcessingUnit(TPU).Theyareputtinganametotheirheterogeneousorhomogeneousarchitecture,whichisnotasingleprocessor.” Alittlehistory Thingsweremuchsimpler40yearsago.Therewasthecentralprocessingunit(CPU),andwhilethereweremanyvariantsofit,theywereallfundamentallyvonNeumanarchitecture,Turingcompleteprocessors.Eachhaddifferentinstructionsetsthatmadethemmoreefficientforcertaintasksandtherewasplentyofdiscussionabouttherelativemeritofcomplexinstructionset(CISC)versusreducedinstructionset(RISC). TheemergenceofRISC-VbroughtalotofattentiontotheISA.“PeoplewanttounderstandtheISAbecauseitistheISAthatdefineshowoptimizedtheprocessorisforadefinedtask,”saysXilinx’sUhm.“TheycanlookattheISAandstartcountingcycles.IfoneISAhasanativeinstructionandoperatesatonegigahertz,IcancomparethattoanotherprocessorISAwherethesamefunctionmayrequiretwoinstructions,buttheprocessorrunsat1.5gigahertz.Whichonegetsmefurtherahead?Theydothemathfortheimportantfunctionality.” CPUshavebeenpackagedinmanyways,sometimesputtingIOormemoryintothesamepackageandtheywerecalledmicro-controllerunits(MCU). Whenmodemsbecamefashionable,digitalsignalprocessors(DSP)emerged,andtheyweredifferentbecausetheyusedtheHarvardarchitecture.Thatseparatedtheinstructionbusfromthedatabus.SomeofthemalsoimplementedSIMDarchitecturesthatmadedatacrunchingmoreefficient. Theseparationofinstructionsanddatawasdonetoincreasethroughputrates,eventhoughitrestrictedsomefringeprogrammingthatcouldbedone,suchasself-writingprograms.“Often,itisnotcomputethatistheboundarycondition,”saysUhm.“ItisincreasinglytheI/Oormemory.Theindustryswitchedfromjackingupcompute,tomakingsurethatthere’senoughdatatokeepthecomputecrunchingandmaintainperformance.” Whensingleprocessorsstoppedbecomingfaster,multipleprocessorswerelinkedtogether,oftensharingmemoryandmaintainingthenotionthateachprocessor,andthetotalclusterofprocessors,remainTuringcomplete.Itdidn’tmatterwhichcoreanypieceofaprogramwasexecutedon.Theresultwasthesame. Thenextmajordevelopmentwasthegraphicsprocessingunit(GPU),andthisbrokethemoldbecauseeachprocessingelementorpipelinehaditsownmemorythatwasnotaddressableoutsideoftheprocessor.Becausethememorywasfinite,itmeantthatitcouldnotperformanyarbitraryprocessingtask,onlytheonesthatcouldfitintheprovidedmemoryspace. “GPUsareverycapableprocessorsforcertaintypeoffunctions,buttheyhaveextremelylongpipelines,”notesUhm.“ThosepipelineskeeptheGPUunitscrunchingondata,butatsomepoint,ifyouhavetoflushthepipeline,that’sahugehit.Thereisasignificantamountoflatencyandnon-determinismbuiltintothesystem.” Whilemanyotheracceleratorshavebeendefined,theGPU—andlaterthegeneral-purposeGPU(GPGPU)—definedaprogrammingparadigmandsoftwarestackthatmadethemmoreapproachablethanacceleratorsofthepast.“Overtheyears,certainjobshavebeenspecialized,”saysImperas’Davidmann.“TherewastheCPUforsequentialprograms.Therewasthegraphicsprocessor,whichfocusedonmanipulationofdataforascreenandintroducedustoahighlyparallelworld.Taskswereperformedusinglotsoflittleprocessingelements.Andnowtherearemachinelearningtasks.” Whatotherconstructionrulesaretheretobebrokenthatcanexplainallofthenewarchitectures?Inthepastprocessorarrayswereoftenconnectedthroughmemory,orafixednetworktopology,suchasmeshortoroid.Whathasemergedmorerecentlyistheincorporationofanetworkonchip(NoC)thatenablesdistributed,heterogenousprocessorstocommunicateinamoreflexiblemanner.Inthefuture,theyalsomayenablecommunicationswithoutusingmemory. “Atthispoint,NoCsonlycarrydata,”saysArteris’Frank.“Inthefuture,theNoCcouldexpandintootherareaswherecommunicationbetweenacceleratorsgoesbeyonddata.Itcouldsendcommands,itcouldsendnotifications,etc.Thecommunicationneedsofanacceleratorarrayor,seaofaccelerators,mightbedifferentthanthecommunicationneedsof,forexample,CPUsorastandardSoC.Butnetworkonachipdoesnotconstrainyoutojustasubset.Youcanoptimizeandimproveperformancebysupportingspecialcommunicationneedsofaccelerators.” Implementationarchitecture Onewaythatprocessorsdifferentiateisbyoptimizingforaparticularoperatingenvironment.Forexample,softwaremayruninthecloud,butyoumayalsoexecutethesamesoftwareonatinyIoTdevice.Theimplementationarchitecturewillbeverydifferentandachievedifferentoperatingpointsintermsofperformance,power,cost,ortheabilitytooperateunderextremeconditions. “Someapplicationsweretargetedforthecloud,andnowwe’rebringingthemclosertotheedge,”saysCadence’sThomas.“Thismaybebecauseoflatencyrequirements,orforenergyorpowerdissipation,andthatwouldrequireadifferenttypeofarchitecture.Youmaywanttohaveexactlythesamesoftwarestacktobeabletoruninbothlocations.Thecloudneedstoprovideflexibilitybecauseitwillbereceivingdifferenttypesofapplicationsandhastobeabletoaggregateanumberofusers.Thisrequiresthehardwareontheservertobeapplication-specificcapable,butonesizedoesnotfitall.” MLaddsitsownrequirements.“Whenbuildingintelligentsystemswithneuralnetworksandmachinelearning,youneedtoprogramnewnetworksandmapthistohardware,usingsoftwareframeworksandacommonsoftwarestack,”addsThomas.“YoucanthenadaptthesoftwareapplicationtotherighthardwarefromaPPAstandpoint.Thisdrivestheneedfordifferenttypesofprocessingandprocessorstobeabletoaddresstheseneedsatthehardwarelayer.” Thoseneedsaredefinedbytheapplication.“Onecompanyhascreatedaprocessorforgraphoperations,”saysFrank.“Theyoptimizeandacceleratehowtofollowgraphs,anddooperationssuchasreorderingofgraphs.Thereareothersthatmostlyacceleratethebruteforcepartofmachinelearning,whichismatrix-matrixmultiplies.Memoryaccessisaparticularproblemforeacharchitecture,becausewhenyoubuildanaccelerator,themostimportantgoalistokeepitbusy.YouhavetogetasmuchdatathroughtotheALUsasitcanconsumeandproduce.” Manyoftheseapplicationshaveanumberofthingsincommon.“Theyallhavesomelocalmemory,theyhaveanetworkonchiptocommunicatethingsaround,andeachprocessor,whichexecutesasoftwarealgorithm,iscrunchingonasmallchunkofdata,”saysDavidmann.“ThosejobsarescheduledbyanOSwhichrunsonamoreconventionalCPU.” Thetrickybitforhardwaredesignersispredictingwhattasksitwillbeaskedtoperform.“Althoughyou’regoingtohavesimilartypesofoperationinsomeofthelayers,peoplearelookingatdifferentiationinthelayers,”saysThomas.“Tobeabletoprocesstheneuralnetworkrequiredseveraltypesofprocessingcapabilities.Itmeansthatyouneedtobeabletoprocessacertainwayforonepartoftheneuralnetwork,andthenanothertypeofoperationsmayberequiredtoprocessanotherlayer.Thedatamovementandtheamountofdataisalsochanginglayerafterlayer.” Thisdifferentiationcangobeyondthedatamovement.“Forgenomesequencing,youneedtodocertainprocessing,”saysFrank.“Butyoucannotaccelerateeverythingwithasingletypeofaccelerator.Youhavetobuildacompletesetofdifferentacceleratorsforthepipeline.TheCPUsbecometheguardianthatshepherdtheexecutionflow.Itsetsthingsup,doestheDMA,providesthedecision-makingprocessinbetween.Thereisawholearchitecturetasktounderstandandanalyzealgorithmsanddefinehowyouwanttooptimizetheprocessingofthem.” Partofthatprocessrequirespartitioning.“Thereisnosingleprocessortypethat’soptimizedforeverysingleprocessortask—notFPGAs,notCPUs,notGPUs,notDSPs,”saysUhm.“Wecreatedaseriesofdevicesthatcontainallofthose,butthehardpartonthecustomersideisthattheyhavetoprovidetheintelligencetodeterminewhichpartsofthisentiresystemaregoingtobetargetedattheprocessors,orattheprogrammablelogic,orattheAIengines.Everyonewantsthatauto-magicaltool,atoolthatcaninstantlydecidetoputthisontheCPU,putthatontheFPGA,putthatontheGPU.Thattooldoesnotexisttoday.” Still,therealwayswillbearolefortheCPU.“CPUsareneededtoexecutetheirregularpartoftheprogram,”saysFrank.“ThegeneralprogrammabilityoftheCPUhasitsadvantages.Itjustdoesn’tworkwellifyouhavespecializeddatastructuresormathematicaloperations.ACPUisageneralprocessor,anditisnotoptimizedforanything.It’sgoodatnothing.” Changingabstraction Inthepast,thehardware/softwareboundarywasdefinedbytheISA,andthatmemorywascontiguouslyaddressable.Whenmultipleprocessorsexisted,theyweregenerallymemory-coherent. “Coherenceisacontract,”saysFrank.“Itisacontractbetweenagentsthatsays,‘IpromiseyouthatIwillalwaysprovidethelatestdatatoyou.’Coherencebetweenequalpeersisveryimportantandwillnotgoaway.Butyoucouldimaginethatinadataflowengine,coherenceislessimportantbecauseyou’reshippingthedatathatismovingontheedge,directlyfromoneacceleratortotheother.Ifyoupartitionthedataset,coherencegetsinthewaybecauseitcostsyouextracycles.Youhavetolookthingsup.Youhavetoprovidetheupdateinformation.” Thatcallsfordifferentmemoryarchitectures.“Youhavetothinkaboutthememorystructurebecauseyouonlyhavesomuchtightlycoupledmemory,”saysUhm.“Youcouldaccessadjacentmemory,butyouquicklyrunoutofadjacenciestobeabletodothatinatimelyfashion.Thathastobecomprehendedinthedesign.Asthetoolsmature,moreofthatwillstarttobecomeunderstoodbythetools.Todayitisdonebyhumanintelligence,bybeingabletounderstandthearchitectureandapplyit.” Therealsoisaneedforhigherlevelsofabstraction.“Thereareframeworkswhereyoucanmap,orcompile,knownnetworksontotargethardware,”saysThomas.“Youhaveasetoflow-levelkernels,orAPIs,thatwillbeusedinthesoftwarestack,andtheneventuallyusedbythemapperoftheneuralnetwork.Underneath,youmayhavedifferenttypesofhardware,dependingonwhatyouwanttoachieve,dependingonyourproductdetails.Itimplementsthesamefunctionality,butnotwiththesamehardware,notonthesamePPAtradeoff.” Thatputsalotofpressureonthosecompilers.“Themainquestionishowdoyouprogramacceleratorsinthefuture?”asksFrank.“DoyouimplementhardwiredenginesthatarejuststrungtogetherlikethefirstgenerationofGPUs?Ordoyoubuildlittleprogrammableenginesthathavetheirowninstructionset?Andnowyouhavetogoandprogramthesethingsindividuallyandconnecteachoftheseengines,executingtasks,withadataflow.Oneprocessorhassomesubsetofthetotalinstructionset,anotheronehasadifferentsubset,andtheywillallsharesomeoverlappingpartforthecontrolflow.Youmighthavesomethathaveslightlydifferentaccelerationcapabilities.Thecompilers,orthelibrariesthatknowaboutit,mapaccordingly.” Conclusion Thearchitectureofprocessorsisnotchanging.Theystillabidebythesamechoicesthathaveexistedforthepast40years.Whatischangingisthewayinwhichchipsarebeingconstructed.Theynowcontainlargenumbersofheterogeneousprocessorsthathavememoryandcommunicationsoptimizedforasubsetofapplicationtasks.Eachchiphasmadedifferentchoicesabouttheprocessorcapabilitiesandwhattheyareoptimizedfor,abouttherequireddatathroughput,andaboutthedataflowsthattypicallywillbeseen. Everyhardwareproviderwantstodifferentiateitschipfromtheothers,butthat’saloteasiertodothatbybrandingthanbytalkingaboutthetechnicaldetailsoftheinternals.Andsotheygiveitanameandcallitthefirst,thefastest,thelargest,andtieittoaparticulartypeofapplicationproblem.Thethreeletteracronymshavebecomeapplicationtasknames,buttheydonotdefinethehardwarearchitecture. Related ChallengesForNewAIProcessorArchitectures GettinganAIseatinthedatacenterisattractingalotofinvestment,buttherearehugeheadwinds. TenLessonsFromThreeGenerationsShapedGoogle’sTPUv4i EvolutionofGoogle’sTPUv4i NewArchitectures,MuchFasterChips Massiveinnovationtodriveordersofmagnitudeimprovementsinperformance. ImprovingMedicalImageProcessingWithAI Faster,smarterimagingopensdoorstoeverythingfrom4Dmodelingandhigherresolutionwithlessnoise. Tags:architecturesArterisIPCadenceCadenceDesignSystemsCPUDSPFPGAGPUHarvardarchitectureImperasSoftwareIPUMCUnetworkonchipNPUprocessorsSIMDTPUTuringcompleteXilinx BrianBailey  (allposts) BrianBaileyisTechnologyEditor/EDAforSemiconductorEngineering. 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